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Analog/Mixed-Mixed Signal Layout Design Engineer
Posted: 09/07/2026
Industry: Engineering and Technical
Job Number: 19529
Security Clearance: ACTIVE - Secret
Work Model: Remote
Job Description
Analog/Mixed-Mixed Signal Layout Design Engineer.
Duration: 3 years
Pay Range: $70-$90/hr.
This is part-time, up to 24 hours per week
Clearance: Active Secret required
Responsibilities include but are not limited to.
• Physical layout and verification of integrated circuit building blocks
• Full-chip assembly and top-level verification.
• Use best-practices for managing local process variation through layout techniques as well as high-speed digital and RF layout techniques to minimize unwanted parasitic interactions.
Must Have:
• Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in multiple foundries such as Global Foundries, onsemi and Tower Jazz
• Cadence integrated circuit design flow including layout, DRC, LVS and parasitic extraction through the use of Calibre and Assura.
• Proven track record of multiple design tape outs
• Extensive experience in top level floor planning as well as block level design
• Strong interpersonal and organizational skills along with strong written/verbal skills are required to support a multi-person design team in an effective way.
Work from Home:
This position is REMOTE. The candidate is able to work remotely from any location. They may be asked to take up to 3+ trips per calendar year to Lexington if the program/project requires it.
Hours:
This position is a part time role with up to 24hrs a week.
Clearance:
An ACTIVE clearance is required for this role. Do not submit candidates who do not meet this requirement.
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Duration: 3 years
Pay Range: $70-$90/hr.
This is part-time, up to 24 hours per week
Clearance: Active Secret required
Responsibilities include but are not limited to.
• Physical layout and verification of integrated circuit building blocks
• Full-chip assembly and top-level verification.
• Use best-practices for managing local process variation through layout techniques as well as high-speed digital and RF layout techniques to minimize unwanted parasitic interactions.
Must Have:
• Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in multiple foundries such as Global Foundries, onsemi and Tower Jazz
• Cadence integrated circuit design flow including layout, DRC, LVS and parasitic extraction through the use of Calibre and Assura.
• Proven track record of multiple design tape outs
• Extensive experience in top level floor planning as well as block level design
• Strong interpersonal and organizational skills along with strong written/verbal skills are required to support a multi-person design team in an effective way.
Work from Home:
This position is REMOTE. The candidate is able to work remotely from any location. They may be asked to take up to 3+ trips per calendar year to Lexington if the program/project requires it.
Hours:
This position is a part time role with up to 24hrs a week.
Clearance:
An ACTIVE clearance is required for this role. Do not submit candidates who do not meet this requirement.
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| Must Have | |
|---|---|
| Design | |
| Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura | 10Â years |
| Eexperience in top level floor planning as well as block level design | 10Â years |
| Electrical/Electronics | |
| Experience with multiple design tape outs | 10Â years |
| Experience | |
| Currently holds a Secret Clearance (OR a higher clearance) | Yes |
| Deep-submicron CMOS Layout (12nm - 22nm, Global Foundries) | 10Â years |
| Soft Skills | |
| Presentation, verbal and written communication skills | Yes |
| Strong team communication | Yes |
| Strong Verbal and Written Communication | Yes |
Job Requirements
Calibre, CMOS, Tower Jazz, DRC, LVS, Assura